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AP3302 Pt3 Contents

AP3302 Pt3 Section 2Contents

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AP 3302 Pt. 3

Section 2


Frequency-Dividing & Counting Circuits

It will be noted that one half-cycle of each cycle of the multivibrator output is still free-running. This may give rise to instability if the circuit conditions change to cause V2g to reach cut-off earlier or later than the required instant of time. If V2g reaches cut-off earlier than normal then V1 may be triggered by pulse 3. If V2 cut-on is delayed, V1 may not be triggered until pulse 1 in the next period. To improve the stability the trigger pulses may be applied to both grids and the circuit adjusted such that pulse 2 triggers V2 and pulse 4, V1. In this way we ensure that the triggering times remain stable. For an even count-down ratio it also ensures that the output square wave is symmetrical. This may be a requirement.

This circuit is capable of dividing by up to as much as ten times. At higher count-down ratios the exponential rise of the grid voltage becomes too ‘flat’ near cut-off to ensure reliable switching by the correct trigger pulse (Fig 4). Increasing the positive aiming voltage may improve this but the available time period is then reduced so that this in itself limits high count-down ratios.

We know that an astable multivibrator will continue to free-run in the absence of trigger pulses. This is a disadvantage in some circuits because it is often better that failure should cause a null output than an incorrect one. When this is the requirement a monostable multivibrator (flip-flop) may be used as the frequency divider (Fig 5). The flip-flop reverts to its stable state after a relaxation period and will not operate in the absence of trigger pulses. In Fig 5 TR2 is normally conducting and TR1 is cut off by the positive bias applied to its base. The input applied to the trigger circuit (C1, R1, D1) causes negative-going trigger pulses to be applied to TR1 base. The first pulse (pulse number 5) cuts on TR1 and the usual avalanche occurs to switch off TR2. Vc1 therefore falls to just above zero volts and Vc2 rises to just below the negative supply voltage level (determined by the values of RL2, R3, R4).


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